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Firm Details
Firm: Pacific Microchip Corporation
Address: 3916 Sepulveda Boulevard, #108, Culver City, CA, 90230-4650
URL: N/A
EIN: 204998377
DUNS: 831566877
CAGE: 5MSR9
See All Awards for this Firm
Firm Ownership Status
Disadvantaged-Owned: No
Woman-Owned: No
Hubzone-Owned: No
Veteran-Owned: No
Disabled Veteran-Owned: No

Award Details
Proposal #: S1.03-8314
Title: Low-power Cross-Correlator ASIC
Contract #: NNX13CP01C
Program/Year/Phase/Center: SBIR 2011 -2 (N/A)
Start/End Date: 01/02/2013 - N/A
Award Amount: $950,000.00
Subtopic: S1.03 -Passive Microwave Technologies
Associated Awards:
View Phase 1 Award

Principal Investigator Business Official
Name: Denis Zelenin
Phone:    (310) 683-2628
Email: denis@pacificmicrochip.com
Name: Dalius Baranauskas
Phone:    (310) 683-2628
Email: dalius@pacificmicrochip.com

Abstract
The NASA's PATH mission includes the GeoSTAR satellite that carries aboard a microwave sounder employing an array of 375 microwave antennas with corresponding receivers. Each receiver is tuned to the 180GHz frequency, while the intermediate frequency (IF) reaches 500MHz. The IF signal is quantized at 1GHz with 2-bit accuracy. The resulting data rate is 700Gb/s. This data has to be pre-processed aboard the satellite before it can be transmitted to Earth for further processing. One of the steps of such data processing is cross-correlation. For a space borne instrument, power dissipation and radiation hardness are among the most important requirements. Pacific Microchip Corp. is designing an ASIC that includes a cross-correlation unit with interfaces for the GeoSTAR's receivers. The ASIC will have greatly reduced power consumption compared to that of the FPGA-based or classic ASIC-based implementations. This ASIC must be designed and integrated with already existing system components of the GeoSTAR instrument. The ASIC includes cross-correlation cells based on novel architecture. The deep submicron SOI CMOS technology selected for the ASIC's fabrication will increase its tolerance to the total ionizing dose (TID) and reduce the probability of radiation-induced latch-up. The design of the ASIC will follow design for testability (DFT) methods, which will simplify characterization and testing of the fabricated ASIC, reduce risk and lower the cost of the product.

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Related Documents
Proposal Briefing Chart
Final Summary Chart





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