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Firm Details
Firm: Pacific Microchip Corporation
Address: 3916 Sepulveda Boulevard, #108, Culver City, CA, 90230-4650
URL: N/A
EIN: 204998377
DUNS: 831566877
CAGE: 5MSR9
See All Awards for this Firm
Firm Ownership Status
Disadvantaged-Owned: No
Woman-Owned: No
Hubzone-Owned: No
Veteran-Owned: No
Disabled Veteran-Owned: No

Award Details
Proposal #: S1.03-8314
Title: Low-power Cross-Correlator ASIC
Contract #: NNX12CE50P
Program/Year/Phase/Center: SBIR 2011 -1 (N/A)
Start/End Date: 02/13/2012 - N/A
Award Amount: $124,971.00
Subtopic: S1.03 -Passive Microwave Technologies
Associated Awards:
View Phase 2 Award

Principal Investigator Business Official
Name: Denis Zelenin
Phone:    (310) 683-2628
Email: Denis@PacificMicrochip.com
Name: Dalius Baranauskas
Phone:    (310) 683-2628
Email: dalius@pacificmicrochip.com

Abstract
Pacific MicroCHIP Corp. offers to design an ASIC that includes a cross-correlation unit together with the interfaces to be connected to the output of the GeoSTAR's receivers, multiplexer and output interface for the GeoSTAR's system-level integration. The proposed novel ASIC required by NASA's PATH mission will have a greatly reduced power consumption compared to a FPGA based or a classic ASIC based implementations, increased radiation hardness and extended operating temperature range. The proposed cross-correlation unit consists of cross-correlation cells which are based on novel architecture. The logic primitives are arranged to "work when must" rather than to "work when need" in these novel cross-correlation cells. The high speed interfaces the proposed ASIC will incorporate can minimize the power consumption and increase the reliability. Termination resistors, amplifiers, analog-to-digital-converters realized inside the ASIC will save power due to shorter interconnects compared to interconnects that are used in FPGAs. Moreover, the high-speed receivers-deserializers could further save the power due to reduced number of termination resistors compared to the high-speed interface with analog-to-digital converters. The deep submicron SOI CMOS technology selected for the ASIC's fabrication will increase its tolerance to total ionizing dose (TID) and reduce the probability of radiation induced latch-up. The ASIC will be designed following the design for testability (DFT) methods that will simplify characterization and testing of the fabricated ASIC thus will reduce the risk and lower the cost of the product.
Phase I of the project will provide a complete definition of the proposed ASIC, its design and in silico validation of critical circuits. Phase II will produce a fieldable product ready for commercialization in Phase III.

Taxonomy Mappings
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Related Documents
Proposal Briefing Chart
Final Summary Chart





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